The present invention relates generally to capacitors for integrated circuits, and more particularly to stacking thin-dielectric decoupling capacitors for integrated circuits showing high unit capacitance.
In a normal configuration of semiconductor chips, power lines and ground lines are routed to logic gates in integrated circuits. The current from power supply flows through power lines, logic gates, and finally to ground. During the switching of the logic gates, a large amount of changes in the current occurs within a short period of time. Decoupling capacitors are used to absorb these glitches during current switching and to maintain a constant voltage between supply voltage and ground. Good decoupling capacitors should show high capacitance per unit area, low leakage current and short time constant. There are three kinds of conventional decoupling capacitors commonly used in integrated circuits, namely inter-digital fringing metal or poly capacitors, area Metal-Isolator-Metal (MiM) capacitors, area Poly-Isolator-Poly (PIP) capacitors and thin-dielectric capacitors.
FIG. 1(a) presents a top view of an inter-digital fringing capacitor. The inter-digital fringing capacitors are formed in the same metal layer with multiple-finger electrodes. The capacitance of an inter-digital fringing capacitor is determined by the spaces between these electrodes and density of the electrodes. The time constant of inter-digital fringing capacitors is very short. However, because the minimum metal-to-metal space is limited, the unit capacitance is low. The inter-digital fringing capacitors are commonly made of metal or poly.
FIG. 1(b) presents a cross-sectional view of an MiM capacitor. An MiM capacitor comprises two conductive metal layers and a dielectric isolator layer. The capacitance is formed between these two conductive metal layers. MiM capacitors can achieve both high unit capacitance and fast time constant. But this structure requires additional masks in fabrication to make unit capacitance high which requires more complicated processing techniques. Similarly, Poly-Insolator-Poly, or Poly-Insolator-Metal capacitors are other variations.
FIG. 1(c) presents a cross-sectional view of a thin-dielectric capacitor. The thin-dielectric capacitor can achieve the highest unit capacitance among the three kinds of conventional decoupling capacitors. But the time constant may be too long for high speed switching. Besides, the thin gate oxide is constantly biased at power supply voltage. This may create oxide integrity problems when the gate oxide thickness is less than 50 Å. As the oxide thickness becomes thinner with today's fabrication techniques, these issues, including stress failure and high leakage current, become significant. Also, if the capacitor is near an I/O pad, the electrostatic discharge (ESD) may cause the oxide breakdown.
Desirable in the art is an improved capacitor design that would improve upon the conventional thin-dielectric capacitor design.